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IBM 5nm Transistor |
This new method, created in tandem with research partners GLOBALFOUNDRIES and Samsung, changes some basic things about how chips are put together, and helps break a barrier with the previous process that essentially signaled the end of Moore’s Law.
The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan . The device structure of the transistor, known as GAA (gate-all-around) transistor. The 5nm nail sized test chip so created packs 30 billion transistors.
Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.
IBM claims that chips based on this new design can have 40 percent performance gains over the 10nm chips currently in production, at the same level of power. Or, more interestingly, up 75 percent power savings at the current generation's level of performance. The new EUV lithography (Extreme Ultraviolet) process used here also allows for nanosheet width to be adjusted continuously in a single chip design, which means circuits can be fine-tuned for power and performance in one manufacturing pass.
Due to this 5nm technology the battery life is getting increased . The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.
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